The present invention pertains to the field of integrated circuit design. More particularly, the present invention relates to a circuit to place a device in a forward conducting state during transient power supply overvoltage events and to turn the device off during normal operation.
On an integrated circuit chip, power rails are typically used to supply power to the chip. The power rails may comprise a positive power source Vcc and a ground Vss. Ideally, the power rails provide constant, steady voltages to the chip. Noise on the power rails, however, may cause voltage spikes or overvoltage on the Vcc network. Transient voltage on the Vcc network is a typical electrostatic discharge (ESD) event. ESD is potentially dangerous to transistors on an integrated circuit. Thus, overvoltage protection circuits are used to help discharge ESD events.
One example of an ESD overvoltage protection circuit is depicted in FIG. 1. The circuit includes power rails Vcc 100 and Vss 105, a timer circuit comprising resistor 110 and capacitor 120, a first inverter comprising transistors 130 and 140 coupled to the timer circuit, a second inverter comprising transistors 150 and 160 coupled to the first inverter, a capacitor 170 coupled to the second inverter, and a transistor 180 coupled to capacitor 170. The transistor 180 is typically a large PMOS device.
In normal operation, node 125 is held high by the timer circuit. The first inverter inverts the signal of node 125 and outputs an active low signal at node 155. The second inverter then inverts the active low signal of node 155 and outputs an active high signal at node 175. Because the node 175 is active high in normal operation, the transistor 180 is turned off.
During a voltage transient on Vcc 100, the first inverter is toggled and outputs an active high signal at node 155. The second inverter is also toggled and outputs an active low signal at node 175, turning on transistor 180. The transistor 180, being a large PMOS transistor, is capable of shunting a large amount of current between power rails Vcc 100 and Vss 105, which helps to discharge the ESD event. As the overvoltage is reduced, the inverters revert back to their normal logic levels and turn the transistor 180 off.
The transistor 180, however, may be an appreciable source of leakage current between power rails Vcc 100 and Vss 105 during normal operation. The current trend in integrated circuit deign in CMOS technologies is toward ultra thin gate oxides, which tends to create higher levels of gate and subthreshold leakage. A typical product may have dozens of power supply clamps placed throughout the die. This can be problematic for power constrained or low-power applications. Therefore, a power clamping circuit that reduces standby leakage is desired.